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A 16-bit 125 MS/s pipeline analog-to-digital converter (ADC) implemented in a 0.18 Â¿m CMOS process is presented in this paper. A SHA-less 4-bit front-end is used to achieve low power and minimize the size of the input sampling capacitance in order to ease drivability. The ADC includes foreground factory digital calibration to correct for capacitor mismatches and dithering that can be optionally enabled to improve small-signal linearity. This ADC achieves an SNR of 78.7 dB, an SNDR of 78.6 dB and an SFDR of 96 dB with a 30 MHz input signal, while maintaining an SNR > 76 dB and an SFDR > 85 dB up to 150 MHz input signals. Further, with dithering enabled the worst spur is <-98 dB for inputs below -4 dBFS at 100 MHz IF. The ADC consumes 385 mW from a 1.8 V supply.