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A Piecewise Linear 10 Bit DAC Architecture With Drain Current Modulation for Compact LCD Driver ICs

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7 Author(s)
Yong-Joon Jeon ; Dept. of Electr. Eng. & Comput. Sci., KAIST, Daejeon, South Korea ; Hyung-Min Lee ; Sung-Woo Lee ; Gyu-Hyeong Cho
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A piecewise linear 10 bit DAC for LCD data driver with robust interpolation method of drain current modulation is presented. It has higher effective bit resolution than the linear 10 bit switched-capacitor DAC when applied to nonlinear liquid crystal characteristics. By adopting a simultaneous design flow based on the estimations for the mismatch and nonlinearity effects on channel driver performance, the proposed DAC accomplishes good DNL of 0.37 LSB and excellent channel uniformity such that the mean and the standard deviation of the maximum output voltage deviations are 6.35 mV and 0.54 mV, respectively. The data driver with the new interpolation shows 8.2% shrinkage of chip area in comparison with the conventional 8 bit data driver with R-DAC.

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IEEE Journal of Solid-State Circuits  (Volume:44 ,  Issue: 12 )