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Low-power split-path data-driven dynamic logic

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5 Author(s)
F. Frustaci ; Department of Electronics, Computer Science and Systems, University of Calabria, Arcavacata di Rende ¿ 87036, Rende (CS), Italy. ; M. Lanuzza ; P. Zicari ; S. Perri
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Data-pre-charged dynamic logic, also known as data-driven dynamic logic (D3L), is very efficient when low-power constraints are mandatory. Differently from conventional dynamic domino logic, which exploits a clock signal, D3L uses a subset of the input data signals for pre-charging the dynamic node, thus avoiding the clock distribution network. Power consumption is significantly reduced, but the pre-charge propagation path delay affects the speed performances and limits the energy-delay product (EDP) improvements. This study presents a new dynamic logic named split-path D3L (SPD3L) that overcomes the speed limitations of D3L. When applied to a 16 times 16 bit booth multiplier realised with STMicroelectronics 65 nm IV CMOS technology, the proposed technique leads to an EDP 25 and 30% lower than standard dynamic domino logic and conventional D3L counterparts, respectively.

Published in:

IET Circuits, Devices & Systems  (Volume:3 ,  Issue: 6 )