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Buffer management for shared-memory ATM switches

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2 Author(s)
Mutlu Arpaci ; Georgia Institute of Technology, USA ; John A. Copeland

In the shared-memory switch architecture, output links share a single large memory, in which logical FIFO queues are assigned to each link. Although memory sharing can provide a better queuing performance than physically separated buffers, it requires carefully designed buffer management schemes for a fair and robust operation. This article presents a survey of the buffer management methods that have been proposed for shared-memory packet switches. Several buffer management policies are described, and their strengths and weaknesses are examined. The performances of various policies are evaluated using computer simulations. A comparison of the most important schemes is obtained with the help of the simulation results and the results provided in the literature. The survey concludes with a discussion of the possible future research areas related to shared-memory ATM switches.

Published in:

IEEE Communications Surveys & Tutorials  (Volume:3 ,  Issue: 1 )