By Topic

New layout scheme to improve ESD robustness of I/O buffers in fully-silicided CMOS process

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Ming-Dou Ker ; Inst. of Electron., Nat. Chiao-Tung Univ., Hsin-Chu, Taiwan ; Wen-Yi Chen ; Wuu-Trong Shieh ; I-Ju Wei

Silicidation used in CMOS processes has been reported to result in substantial degradation on ESD robustness of CMOS devices. In this work, a new ballasting layout scheme for fully-silicided I/O buffer is proposed to enhance its ESD robustness. Experimental results from real IC products have confirmed that the new ballasting layout scheme can successfully increase HBM ESD robustness of fully-silicided I/O buffers from 1.5 kV to 7 kV without using the additional silicide-blocking mask.

Published in:

EOS/ESD Symposium, 2009 31st

Date of Conference:

Aug. 30 2009-Sept. 4 2009