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A DRC-based check tool for ESD layout verification

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7 Author(s)
Smedes, T. ; NXP Semicond., Nijmegen, Netherlands ; Trivedi, N. ; Fleurimont, J. ; Huitsing, A.J.
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The growing complexity of IC designs makes verification for ESD correctness increasingly difficult. A useful verification tool, based on specific ESD layout rules and extended with layout connectivity, will be presented. The demonstrated approach is extendable with respect to checks and analysis options. Successful usage has been demonstrated on products.

Published in:

EOS/ESD Symposium, 2009 31st

Date of Conference:

Aug. 30 2009-Sept. 4 2009