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On-chip signal crosstalk is a function of switching activity pattern, coupling parasitics, and signal timing. We propose a simulated annealing (SA)-based high-level synthesis algorithm for crosstalk activity minimization for a given data environment. We target bus-based architectures as the bus-lines have well-defined neighborhood (aggressors). Our objective is to minimize worst case crosstalk patterns by exploring synthesis solutions with correlations that do not result in such worst case patterns. Besides synthesis moves, we also incorporate bus re-ordering and data transfer invert encoding. Experimental results for design under resource as well as latency constraints are promising. For a set of nine DSP benchmarks we reduce up to 75% of bus lines that require no shielding lines. The results also show that the designs synthesized through the proposed framework have an average performance improvement by 23.5% compared to un-optimized designs.
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on (Volume:19 , Issue: 2 )
Date of Publication: Feb. 2011