Skip to Main Content
We revisit the rotary clock scheme in, and firstly propose and analyze the multiple-mode operations of rotary clock structure, which can be utilized to generate multiple clock frequencies within one loop. By replacing original inverter pairs with feed-forward differential buffers and adding U-shape T-line segments, a novel rotary clock scheme is presented to guarantee the directionality of traveling wave in the closed-loop. Design tradeoffs and methodologies are discussed for this novel directional rotary clock and a 3.3 GHz, 30 pF loading rotary clock design example is given. The simulation results show that, the proposed directional rotary clock can at least reduce 34% power compared with fCV2, and achieve lower power dissipation and sharper rising-edge compared with the conventional rotary clock in.