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On-Chip Interconnect Analysis of Performance and Energy Metrics Under Different Design Goals

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6 Author(s)
Ling Zhang ; Dept. of Comput. Sci. & Eng., Univ. of California, San Diego, La lolla, CA, USA ; Yulei Zhang ; Hongyu Chen ; Bo Yao
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As semiconductor process technology scales down, interconnect planning presents ever-greater challenges to designers. In this paper, we analyze, evaluate, and compare various metrics with optimized wire configurations in the contexts of different design criteria: delay minimization, delay-power minimization, and delay2 -power minimization. We show how various design criteria influence the configuration, performance, and power consumption of repeated wires.

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:19 ,  Issue: 3 )