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A digital background calibration technique is proposed to correct gain errors in pipelined analog-to-digital converters (ADCs). The calibration technique performs the error estimation and the adaptive error correction based on the concept of split ADCs. With the 1- or 1.5-bit realization in pipelined stages, capacitor-mismatch errors can be merged with gain errors, and the proposed calibration technique can be utilized. Behavioral simulations show that the signal-to-noise-and-distortion ratio of a 12-bit pipelined ADC with an 8-bit gain accuracy and the capacitor mismatch sigma = 0.125% can be improved from 56.4 to 73.8 dB. The calibration process converges in approximately 200 000 cycles.