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Log-domain CMOS implementation of a class of analog parallel architectures

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2 Author(s)
Goras, L. ; Fac. of Electron., Telecommun. & Inf. Technol., Tech. Univ. Gheorghe Asachi, Iasi, Romania ; Vornicu, I.

Log-domain CMOS implementation of a class of linear continuous in time and discrete in space homogeneous cellular neural network type analog parallel architectures are discussed. The specific feature of the spatio-temporal dynamics of the array is that it exhibits unstable spatial modes - property which can be used for high speed image processing. The dynamics and spatial frequency response of a 1D array at system level and log-domain transistor level implementation are compared.

Published in:

Semiconductor Conference, 2009. CAS 2009. International  (Volume:2 )

Date of Conference:

12-14 Oct. 2009