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Single Event Gate Rupture Testing on 90 nm Bulk CMOS Deep Trench Oxide Capacitors

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3 Author(s)
Reed K. Lawrence ; BAE Syst., Manassas, VA, USA ; Jeffery A. Zimmerman ; Jason F. Ross

Single event gate rupture (SEGR) testing on a deep trench oxide capacitor used for the reduction of single event upsets (SEU) in a 90 nm bulk complementary metal oxide semiconductor (CMOS) technology indicates that SEGR was not detected.

Published in:

2009 IEEE Radiation Effects Data Workshop

Date of Conference:

20-24 July 2009