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Given the increase in the number of wireless standards, software defined radio has emerged as a cost effective way of supporting multiple standards on the same platform architecture. Embedded systems with such platforms need to power efficient and meet the real time constraints of these wireless standards. Register files are known to be power and performance bottlenecks in high performance low power embedded processors. Given the strict power constraints and real-time performance constraints of these applications a comprehensive study of the register file architecture is needed to reach the most optimal architecture. In this paper we perform an in depth analysis on different register file architectures and their configurations for wireless forward error correction algorithms of different wireless standards like 802.11n and 802.16e. We analyze the traditional clustered register file, hierarchical register file, stream register file as well as asymmetrical register files and show that there are various trade-offs between power and performance across these different architectures.