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A new hardware efficient, low power postprocessor architecture is presented in this paper to correct the mismatch errors in time interleaved ADCs. The Least Mean Squares (LMS) algorithm is utilized as correction algorithm to identify the offset and gain mismatches. The proposed architecture uses one processing core for calibrating all parallel channels output codes with reference channel. Increasing in the number of parallel channels in the time interleaved ADC does not considerably affect the required hardware for proposed postprocessor. FPGA synthesis results of the designed postprocessor for 4-channels 10 bit ADC show that in same throughput, 55% and 25% reduction in the resources usage and power consumption is achievable over conventional architecture.
Date of Conference: 7-9 Oct. 2009