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Low-power pre-decoding based viterbi decoder for tail-biting convolutional codes

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4 Author(s)
Abdallah, R.A. ; ECE Dept., Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA ; Seok-Jun Lee ; Goel, M. ; Shanbhag, N.R.

Low-power and high-throughput Viterbi decoder (VD) for tail-biting convolutional codes is presented in this paper. First, a low complexity radix-4 VD with enhanced decoding features such as end-state forcing and best-state trace back is presented. Second, simple pre-decoding is proposed to decrease the runtime of VD, resulting in significant power saving. The design is implemented in 0:9 V TI 45-nm CMOS process at 100 MHz for Long Term Evolution (LTE) as application. More than 90% power saving is achieved with pre-decoding at a throughput of 120 Mbps and 0:2 dB SNR loss for 10-5 frame error rate.

Published in:

Signal Processing Systems, 2009. SiPS 2009. IEEE Workshop on

Date of Conference:

7-9 Oct. 2009