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This paper describes the implementation of theW-CDMA cell search algorithm on a homogeneous general purpose multi-processor system-on-chip architecture. The architecture is composed of nine nodes based on COFFEE RISC cores communicating using hierarchical network-on-chip. The work focuses on the parallelization of the cell search algorithm, enabling execution on different processing nodes, and exploiting the capabilities of the network-on-chip. We achieved a total speed-up of 7.3 X when compared with a single processing core system, taking into account the overhead related with the communication between different nodes. The result is significant since very close to the theoretical maximum of 9 X. Considering the hardware implementation, the target cell search is performed in 104 ms on an FPGA with 75 MHz maximum frequency, and in 40 ms on an ASIC circuit with 200 MHz maximum frequency.