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Pathfinding: A design methodology for fast exploration and optimisation of 3D-stacked integrated circuits

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4 Author(s)
Dragomir Milojevic ; ULB, BEAMS, CP165/57-Qualcomm Inc., 50, Av.F. Roosevelt-5775 Morehouse Dr, B-1050, Brussels-San Diego, CA 92121, Belgium-USA ; Riko Radojcic ; Roger Carpenter ; Pol Marchal

This paper introduces new design methodology and the corresponding EDA tool chain enabling fast design space exploration and high fidelity of results for emerging heterogeneous 3D-stacked integrated circuits. The proposed framework allows designers to easily trade-off between different system level design choices (e.g. functional partitioning), physical design options (e.g. packaging strategies) and/or technology options (e.g. different technology nodes) and understand their impact on typical design parameters such as cost, performance and power. We demonstrate the proposed framework using existing MPSoC for video coding applications. The system is virtually prototyped as traditional 2D and then 3D design. For a 3D version we place the off-chip DRAM memory on the top of the processing die, and consider different packaging options. For different implementation scenarios we quantify typical design parameters showing the benefits of the 3D integration.

Published in:

System-on-Chip, 2009. SOC 2009. International Symposium on

Date of Conference:

5-7 Oct. 2009