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Transitional gate delay detection for combinational circuits using a genetic algorithm

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2 Author(s)
O'Dare, M.J. ; Sch. of Eng., Univ. of Wales Coll. of Cardiff, UK ; Arslan, T.

The authors present a new technique for the generation of test vector-pairs that detect both delay and single stuck-at-fault conditions in digital logic circuits. A genetic algorithm (GA), is used to pursue and extract efficient tests from a complex search space. Results obtained for the ISCAS 1985 benchmark circuits compare favourably with the results of other researchers, even when the genetic system considers both delay and single stuck-at-fault models

Published in:

Electronics Letters  (Volume:32 ,  Issue: 19 )