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A low-power area-efficient 8 bit SAR ADC using dual capacitor arrays for neural microsystems

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2 Author(s)
Sun-Il Chang ; Dept. of Electr. Eng. & Comput. Sci., Univ. of Michigan, Ann Arbor, MI, USA ; Euisik Yoon

We report an area-efficient 8 bit SAR ADC using dual capacitor array banks for brain signal interface microsystems. The proposed ADC consumes 680 nW and the total chip area is 0.035 mm2. We reduced the area and power by a factor of eight when compared with conventional approaches. If we increase the resolution, the area and power reduction factor exponentially increases in our architecture (e.g., a factor of 16 for 10 bit resolution). The measured SNDR, SFDR, THD, and ENOB are 42.82 plusmn 0.47 dB, 57.90 plusmn 2.82 dB, -53.58 plusmn 2.15 dB, and 6.65 plusmn 0.07 bits, respectively.

Published in:

Engineering in Medicine and Biology Society, 2009. EMBC 2009. Annual International Conference of the IEEE

Date of Conference:

3-6 Sept. 2009