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An empirical large-signal III-V field-effect transistor (FET) model has been developed. Three improved drain-source current (I-V) modeling equations capable of representing arbitrarily shaped transconductance (Gm) curves are proposed from level-1 to level-3. These models are characterized by the static dc and the multibias pulsed I-V measurements along with their dependences on temperature, so as to account for the frequency dispersion and the self-heating effects. By partitioning the Gm plots into five regions, specific parameters of the various model levels can be directly associated with the regions. Besides, the fitting parameters have inherent consistent definitions among different model levels, where some of the key model parameters can be extracted directly from measurements. For the gate-charge formulation (Q-V), a novel charge-conservative gate charge model is presented to accurately trace the nonlinear gate-source (C gs) and gate-drain (C gd) capacitance values. The comprehensive large-signal model is then validated by comparing the predicted I-V, C-V, S-parameters as well as power characteristics with the measured results of III-V FETs.