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This paper presents a modeling strategy to simulate 2D propagation of electrical perturbations induced by direct biasing of substrate junctions. Identifying parasitic substrate devices such as bipolar transistors reaches rapidly its limit when multiple current paths exist as in two-dimensional devices. In this work, we propose to map the substrate using only PN junctions and diffusion resistances. The model of these components has been extended in order to satisfy the majority and minority carrier continuity equation at the boundary of the component. A typical 2D parasitic structure has been simulated and the results are in good agreements with finite element simulation. The proposed approach reduces drastically the time needed to simulate a complex structure such as a whole IC substrate.