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Efficient Don't Care Filling for Power Reduction during Testing

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2 Author(s)
Kundu, S. ; Dept. of Electron. & Electr. Commun., Indian Inst. of Technol. Kharagpur, Kharagpur, India ; Chattopadhyay, S.

Power consumption during test mode is much higher than in normal mode of operation. This paper addresses issue of assigning suitable values to the unspecified bits (don't care) in the test patterns so that both static and dynamic power consumption during testing is reduced. We have used a genetic algorithm based heuristic to fill the don't cares. Our approach produces an average percentage improvement of 31.9, 37.0, and 37.7 in dynamic power and 3.0, 7.4, and 5.3 leakage power over 0-fill, 1-fill, and MT-fill algorithms for don't care filling, considering the test patterns having unspecified bits in ISCAS'89 benchmark suite.

Published in:

Advances in Recent Technologies in Communication and Computing, 2009. ARTCom '09. International Conference on

Date of Conference:

27-28 Oct. 2009