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Low power and high speed requirement is a challenging task in design of ALUs. Supply voltage scaling is promising approach because it reduces switching activities and active power but it degrades the performance and robustness. Recently a new like static circuit family called Feedback-Switch Logic (FSL) has been proposed. FSL is suitable for high speed and low power because it offers fast switching, reduced capacitance and input-switching dependent activity factor without the need of clock connection. This paper presents design of low power high speed 32-bit ALU based on static CMOS and FSL logics at 90 nm CMOS process in CADENCE design tool. Simulation results shows that the design of ALU using FSL achieves 14% reduction in delay but at the cost of 8% increased power consumption compared to static dynamic CMOS logic.
Date of Conference: 27-28 Oct. 2009