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A technique to implement time-interleaved digital DeltaSigma modulators using standard cells and digital synthesis tools is presented. Time interleaving allows clocking of the standard cell blocks at submultiples of the final sampling rate fs. Additional delay stages are used to segment the time-interleaved/pipelined MASH DeltaSigma topology into reduced complexity sub-blocks, each with independent critical paths. A prototype IC has been fabricated in digital CMOS 45 nm-LP: it has been validated at 2.5 GHz, while consuming 6.9 mW from a 1.1 V supply, and at 3.3 GHz increasing the nominal supply to 1.2 V.