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In this paper, the design and analysis of CMOS multicascode configuration with noise reduction topology are proposed. Two low power and miniature low-noise amplifiers (LNAs) were designed and fabricated for demonstration. One with cascode device was designed at V -band in 65-nm process, and the other with triple-cascode structure was fabricated at Q -band in 0.13-?? m technology. To minimize the noise figure and maximize the small-signal gain, inductors are designed and placed between transistors of the cascode and triple-cascode configurations. Based on this approach, the Q-band LNA has a gain of 14.3 dB and a noise figure of 3.8 dB at 38 GHz, with a power consumption of 28.8 mW. The V-band LNA presents a gain of 14.4 dB and a noise figure of 4.5 dB at 54.5 GHz, with a power consumption of 10 mW. The chip size of the V- and Q-band LNAs are 0.55 ?? 0.45 mm2 and 0.42 ?? 0.6 mm2, including all the testing pads. Compared with the conventional cascode LNAs, the proposed cascode LNA shows better noise figure and lower power consumption whereas the triple-cascode LNA features higher gain performance.