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Intermediate Level FPGA Reconfiguration for an Online EHW Pattern Recognition System

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3 Author(s)
Glette, K. ; Dept. of Inf., Univ. of Oslo, Oslo, Norway ; Torresen, J. ; Hovin, M.

We propose a field programmable gate array (FPGA) implementation for a run-time adaptable evolvable hardware classifier system. Previous implementations have been based on a high-level virtual reconfigurable circuit technique which requires many FPGA resources. We therefore apply an intermediate level reconfiguration technique which consists of using the FPGA lookup tables as shift registers for reconfiguration purposes. This leads to significant resource savings, reducing the classifier circuit size to less than one third of the original implementation. This in turn has made it possible to implement a larger, more accurate classifier than before, giving 97.5% recognition accuracy for a face image application. Experiments also show that a reduction of data element resolution can lead to further resource savings while still maintaining high classification accuracy.

Published in:

Adaptive Hardware and Systems, 2009. AHS 2009. NASA/ESA Conference on

Date of Conference:

July 29 2009-Aug. 1 2009