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Dynamically Adapted Low-Energy Fault Tolerant Processors

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2 Author(s)
Pereira, M.M. ; Inst. de Inf., Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil ; Carro, L.

The constant advances on scaling have introduced several issues to the design of processing structures in new technologies. The closer one gets to nano-scale devices, the more necessary are methods to develop circuits that are able to tolerate high defect densities. At the same time, beyond area costs, there is a pressure to maintain energy and power dissipation at acceptable levels, which practically forbids classical redundancy. This paper presents a dynamic solution to provide reliability and reduce energy of a microprocessor using a dynamically adaptive reconfigurable fabric. The approach combines the binary translation mechanism with the sleep transistor technique to ensure graceful degradation for software applications, while at the same time can reduce energy by shutting off the power supply of the unused and the defective resources of a reconfigurable fabric.

Published in:

Adaptive Hardware and Systems, 2009. AHS 2009. NASA/ESA Conference on

Date of Conference:

July 29 2009-Aug. 1 2009

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