By Topic

An efficient memory system for the SIMD construction of a Gaussian pyramid

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Won Park, Jong ; Dept. of Inf. Commun. Eng., Chung Nam Nat. Univ., Taejon, South Korea ; Harper, David T.

In this paper, a memory system is introduced for the efficient construction of a Gaussian pyramid. The memory system consists of an address calculating circuit, an address routing circuit, a memory module selection circuit, and 2n+1 memory modules. The memory system provides parallel access to 2n image points whose patterns are a block, a row or a column, where the interval of the column and the block is 1 and the interval of the row is 2l,l⩾0. The performance of a generic SIMD (single-instruction multiple-data) processor using the proposed memory system is compared with one using an interleaved memory system for the construction of a Gaussian pyramid. The ratio of the time of the construction of level 2 and level 10 from the original image (level 0) of an SIMD processor with an interleaved memory system to that of the proposed memory system is 1.485 and 1.633, respectively

Published in:

Parallel and Distributed Systems, IEEE Transactions on  (Volume:7 ,  Issue: 8 )