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Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC

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4 Author(s)
Ming-Dou Ker ; Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Chung-Yu Wu, Ph.D. ; Tao Cheng ; Hun-Hsien Chang

Capacitor-couple technique used to lower snapback-trigger voltage and to ensure uniform ESD current distribution in deep-submicron CMOS on-chip ESD protection circuit is proposed. The coupling capacitor is realized by a poly layer right under the wire-bonding metal pad without increasing extra layout area to the pad. A timing-original design model has been derived to calculate the capacitor-couple efficiency of this proposed ESD protection circuit. Using this capacitor-couple ESD protection circuit, the thinner gate oxide of CMOS devices in deep-submicron low-voltage CMOS ASIC can be effectively protected.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:4 ,  Issue: 3 )