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This paper presents a power amplifier in 45 nm CMOS technology operating in the 50 to 60-GHz frequency range. It uses a single-ended topology with two cascode stages. A gain of 19.6 dB is obtained at 54 GHz where the gain peaks, and 17 dB at 60 GHz. The measured output-referred 1-dB compression point is 8.7 dBm at 60 GHz and a supply voltage of 2.1 V, and the saturated output power is 13.5 dBm. The bias conditions are shown to be reliable through lifetime measurements. The active chip-area measures 160 mum xtimes 110 mum.