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Ultra-Low-Power 500-MSPS 12-bit A/D Converter Using Interleaving and CMOS Charge-Domain Technology

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2 Author(s)
Michael P. Anthony ; Intersil Corp., Woburn, MA, USA ; G. Sollner

A 12-bit analog-to-digital converter (ADC) has been developed using a unique charge-domain method of handling the analog signals. By interleaving two 250-MS/s unit ADCs on a single chip, an aggregate sample rate of 500 MS/s is achieved. Performance is comparable or superior to all existing ADCs at this sample rate, with power consumption less than 1/5th of that needed by other available designs. Signal-to-noise ratio (SNR) of 65.6 dBFS and spurious-free dynamic range (SFDR) of 78 dBc are obtained at an input frequency of 250 MHz. Total power consumption is 432 mW from a single 1.8-V supply. Added sampling jitter is 60 fs.

Published in:

2009 Annual IEEE Compound Semiconductor Integrated Circuit Symposium

Date of Conference:

11-14 Oct. 2009