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This paper presents an area-efficient and low-power current-mode logarithmic analog-to-digital converter (LADC) that can be potentially used for large-scale CMOS sensor array applications. The core of the proposed LADC consists of a novel analog functional block and a reference transistor working in the subthreshold region, which encodes the input sensor currents into logarithmically compressed voltage outputs. The LADC core has been implemented in standard 0.18 Â¿m CMOS process with a total area of 55 Â¿m Ã 55 Â¿m and a power consumption of less than 9.7 Â¿W. A 7-bit digital counter and an external discrete ramp generator, typically shared among all sensor unit cells in the future sensor array implementation, complete the LADC configuration. Measurement results have presented a dynamic range of 80 dB with 5 KS/s conversion rate. The proposed LADC is ideally suited for compact and low-power CMOS biomedical sensor arrays or CMOS image sensor applications.
Date of Publication: Dec. 2009