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A 107.4 dB SNR Multi-Bit Sigma Delta ADC With 1-PPM THD at - 0.12 dB From Full Scale Input

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4 Author(s)
Jian-Yi Wu ; Nat. Semicond. Labs., Santa Clara, CA, USA ; Zhenyong Zhang ; Subramoniam, R. ; Maloberti, F.

A second order sigma delta modulator (SDM) with a 5-bit quantizer has been presented using several novel techniques: simplified DAC arrays for easy implementation, high-order truncation noise shaping for increased tolerance to analog imperfections, and an extended dynamic range for a maximum input signal swing of up to -0.12 dBFS (Full Scale). With truncation filters and a pseudo SDM in the DSP, the truncation and saturation errors are compensated through the DAC arrays and the DSP. The design, fabricated in a 0.18 mum dual gate oxide (DGO) process obtains a signal-to-noise-and-distortion ratio (SNDR) of 105.9 dB and a dynamic range (DR) of 107.4 dB with 31.25-KHz bandwidth at an 8-MHz sampling frequency and a power consumption of 14.7 mW.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:44 ,  Issue: 11 )

Date of Publication:

Nov. 2009

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