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Matching Performance of FinFET Devices With Fin Widths Down to 10 nm

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13 Author(s)
Magnone, P. ; DEIS Dept., Univ. of Calabria, Rende, Italy ; Mercha, A. ; Subramanian, V. ; Parvais, P.
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In this letter, the matching performances of FinFET devices with high-k dielectric, metal gates, and fin widths down to 10 nm are experimentally analyzed. The stochastic variation of threshold voltage and current factor is examined for both p- and n-type FinFETs. An improvement of the matching performance is expected compared to conventional planar bulk devices since the fins are undoped. The impact of line edge roughness and charge density in the high-k dielectric is evaluated in order to understand which physical parameter fluctuation is dominant on the measured matching parameters.

Published in:

Electron Device Letters, IEEE  (Volume:30 ,  Issue: 12 )