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A New Physical \hbox {1}/f Noise Model for Double-Stack High- k Gate-Dielectric MOSFETs

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11 Author(s)
Seung Hyun Song ; Dept. of Electron. & Electr. Eng., Pohang Univ. of Sci. & Technol., Pohang, South Korea ; Choi, Hyun-Sik ; Rock-Hyun Baek ; Gil-Bok Choi
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In this letter, a new physical 1/f noise model is developed for double-stack high-k dielectric MOSFETs. This new model modifies the trapping-time-constant term in multistack unified noise model. Conventional 1/f noise model is built on the simple square potential approximation which did not account the electric field dependence on trapping time constant. The new model takes into account of a resultant tunneling process from the actual sloped potential in order to eliminate the discrepancies of dielectric trap density on the dielectric thickness and the gate bias. Our model successfully predicts 1/f noise data obtained from SiO2/HfO2 double-stack high- k devices with various gate-dielectric thicknesses using a single set of modeling parameter.

Published in:

Electron Device Letters, IEEE  (Volume:30 ,  Issue: 12 )