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With the technology entering the nanodimension, manufacturing processes are less and less reliable, thus drastically impacting the yield. A possible solution to alleviate this problem in the future could consist in using fault-tolerant architectures to tolerate manufacturing defects. In this paper, we consider the classical triple modular redundancy (TMR) as fault-tolerant architecture for yield improvement purposes. Firstly, we compute a set of conditions to be satisfied in order to make use of TMR architectures interesting for yield improvement. Then, we prove that these conditions depend on the testability of the TMR architecture. Thus, we investigate test requirements for TMR architectures and we propose a solution for generating test patterns for this type of architecture. Finally, we propose a new way of implementing the TMR architecture in order to achieve more benefits for yield improvement purpose. This is done by partitioning the logic part and then adding voters between sub-modules. Experimental results are provided on ISCAS'85 and ITC'99 benchmark circuits to demonstrate the efficiency of the proposed approach in terms of yield improvement.
Date of Publication: November 2009