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An embedded 14-bit 800MS/s DAC for direct digital frequency synthesizer in 0.18-μm CMOS

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5 Author(s)
Shuqin Wan ; Dept. of Inf. Technol., Southern Yangtze Univ., Wuxi, China ; Zhenhai Chen ; Zongguang Yu ; Songren Huang
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An embedded 14-bit 1-GS/s digital-to-analog converter for direct digital frequency synthesizer (DDFS) application is presented. The DAC is implemented using a segmented current-steering architecture, with the top 6 bits and the remaining 8 bits. The output stage of dual return-to-zero scheme is used to enhance the dynamic performance of spurious-free dynamic range (SFDR). The DAC core is fabricated in a 1P6M 0.18 mum standard CMOS technology occupies a die area of only 1.6 times 1.5 mm2. The measured differential nonlinearity lies between -0.8 LSB and 0.3LSB, integral nonlinearity lies between -1.5LSB and 1LSB. And the SFDR is 76.47 dB for 80 MHz output at 0.8 GHz sampling clock rate.

Published in:

Applied Superconductivity and Electromagnetic Devices, 2009. ASEMD 2009. International Conference on

Date of Conference:

25-27 Sept. 2009