3D Stacked IC demonstrator using Hybrid Collective Die-to-Wafer bonding with copper Through Silicon Vias (TSV)

In this paper we demonstrate functional 3D circuits obtained by a 3D Stacked IC approach using Die-to-Wafer Hybrid Collective bonding with Cu Through Silicon Vias (TSV). The Cu TSV process is inserted between contact and M1 of our reference 130 nm CMOS process on 200 mm wafers. The top die is thinned down to 25 mum and bonded to the landing wafer by a combination of polymer bonding and copper to copper thermocompression bonding. Top and landing wafers contain CMOS finished with 2 levels of metal in Copper/Oxide. Ring oscillators consisting of inverters distributed over both top and bottom dies interconnected through up to 40 TSVs are used to demonstrate the process. This paper focuses on integration issues solved during process development and electrical characterization of the obtained TSVs.