Cart (Loading....) | Create Account
Close category search window
 

Comparative analysis of two 3D integration implementations of a SAR processor

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Thorolfsson, T. ; Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA ; Melamed, S. ; Charles, G. ; Franzon, P.D.

When designing 3DICs there are five major issues that differ from 2D that must receive special attention: power delivery, thermal density, design for test, clock tree design and floorplanning. Power delivery in 3D must receive special attention as 3D designs have larger supply currents flowing through the package power delivery pins, along with a longer power delivery path than in comparable 2D system. Thermal density is an issue as 3D integrated chips will have more heat density and less capacity to remove heat than a comparable 2D chip. 3D clock tree distribution is much more difficult than in 2D because the most commonly used methodologies and design tools are geared towards 2D designs and process variation between the different tiers makes it harder to keep skew, jitter and power consumption down. Design for test is harder in 3D because 3D vias provide another point of failure and post fabrication repairs such as focused ion beam are more difficult to perform in 3D. Finally, floorplanning is drastically different in 3D than in 2D, and the four aforementioned issues must all be taken into account during 3D floorplanning. In this paper, all five design issues are explored in the context of a high-resolution memory-on-logic synthetic aperture radar (SAR) processor. The SAR processor is chosen specifically as it requires a significant amount of memory bandwidth that is best met with the high I/O bandwidth afforded by a 3D process. The issues are examined in the context of two implementations for two different 3D integration processes. The first implementation was done in MIT Lincoln Laboratory's 3D FDSOI 1.5 V three tier process and is currently in fabrication. The second design is currently in the design stage, and will be fabricated in two tiers of Chartered Semiconductor's 130 nm process 3D integrated with two tiers of high bandwidth DRAM using Tezzaron Semiconductor's vertical interconnection technology.

Published in:

3D System Integration, 2009. 3DIC 2009. IEEE International Conference on

Date of Conference:

28-30 Sept. 2009

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.