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A parallel ADC for high-speed CMOS image processing system with 3D structure

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7 Author(s)
Kiyoyama, K. ; Micro/Nano-Machining Res. & Educ. Center, Tohoku Univ., Sendai, Japan ; Ohara, Y. ; Lee, K.-W. ; Yang, Y.
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In this paper, we describe the fundamental study of a parallel signal processing circuit, which includes a pixel circuit and a parallel analog-to-digital converter (ADC) with hierarchical correlated double sampling (CDS). To realize high speed image capturing sensor, we have proposed a block-parallel signal processing with three-dimensional (3D) structure. Using 3D structure, the different function layers are stacked vertically and interconnected electrically by through-Si vias (TSVs), which can improve sensor performance and signal band width. On the other hand, the fixed pattern noise (FPN), caused by the circuit device variation, becomes a critical challenge. Experiments on the fabricated pixel circuit have been implemented in a single-layer (two-dimensional) 0.18-mum CMOS image sensor technology. With the analog CDS, the FPN of pixel circuit is reduced by 8.6%. To eliminate the FPN of parallel ADC, a digital CDS technique is implemented. The proposed ADC with digital CDS is designed in a two-dimensional 0.18-mum CMOS technology. The ADC design, including an 8-bit memory, a 6-bit memory, a subtraction circuit, and a comparator, occupies 100times100 mum2 area and 0.9 mW with supply voltage 1.8 V and 1 MS/s conversion rate. The functional simulation and measurement results confirm that our techniques can effectively reduce fixed pattern noise.

Published in:

3D System Integration, 2009. 3DIC 2009. IEEE International Conference on

Date of Conference:

28-30 Sept. 2009

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