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Through Silicon Via(TSV) defect/pinhole self test circuit for 3D-IC

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5 Author(s)
Menglin Tsai ; Electr. & Comput. Eng. Dept., North Carolina State Univ., Raleigh, NC, USA ; Klooz, A. ; Leonard, A. ; Appel, J.
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The next generation of ICs will have greater density and speed than that of their predecessors due to the fact that they can be stacked into 3DICs. A common defect in this emerging technology, however, is that pinholes can form during the process of oxide deposition along the through silicon via (TSV) walls. In this paper, four analog test circuits are explored for the purposes of detecting these pinholes. Each of the circuits uses the leakage current from a single PMOS. By using this leakage current to test the resistance between the TSV and ground, one can determine whether there is a pinhole creating a short between the TSV and the substrate.

Published in:

3D System Integration, 2009. 3DIC 2009. IEEE International Conference on

Date of Conference:

28-30 Sept. 2009

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