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Advanced 3D chip stack process for thin dies with fine pitch bumps using pre-applied inter chip fill

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2 Author(s)
Horibe, A. ; Assoc. of Super-Adv. Electron. Technol. (ASET), Yamato, Japan ; Yamada, F.

A novel stack joining process using newly designed pre-applied underfill for specifically 3D stacked chip was developed. The 3D chip stack process using this technique enables process time reduction and improvement of 3D device reliability because the multi stacked chip experiences only one soldering temperature cycle for joining.

Published in:

3D System Integration, 2009. 3DIC 2009. IEEE International Conference on

Date of Conference:

28-30 Sept. 2009

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