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Fabrication and packaging of microbump interconnections for 3D TSV

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5 Author(s)
Seung Wook Yoon ; STATS ChipPAC Ltd., Singapore, Singapore ; Jae Hoon Ku ; Suthiwongsunthorn, N. ; Marimuthu, P.C.
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Memory bandwidth has become a bottleneck to processor performance for tera-scale computing needs. To reduce this obstacle, a revolution in package technologies is required for tera-scale computing requirements. 3D TSV (Through Silicon Via) stacking is believed to be one of the technologies that can meet those requirements. In advanced 3D stacking technologies, one of the important steps is to develop and assemble fine pitch, high density solder microbumps. This type of solder microbump in flip chip interconnection provides a high wiring density in silicon die with a high-performance signal and power connection. There is a growing interest in the development and study of this new type of chip stacking and bonding approach for both existing and future devices. This paper will highlight the developments of ultra fine pitch and high density solder microbumps for advanced 3D stacking technologies. A Cu/SnAg solder microbump with 50/40 mum in pitch was fabricated at the silicon wafer level by an electroplating method. The total thickness of the plated Cu and SnAg microbump was 20 um. The under bump metallurgy (UBM) layer on the Si carrier used thin film based metal layers. The assembly of the Si chip and the Si carrier was conducted with the thermocompression flip chip bonder at different temperatures, times and pressures and the optimized bonding conditions were obtained. After assembly, the underfill process was carried out to fill the gap and achieve a void free underfilling using a material with a fine filler size. Finally, various reliability tests were carried out for mechanical characterization of microbump interconnections.

Published in:

3D System Integration, 2009. 3DIC 2009. IEEE International Conference on

Date of Conference:

28-30 Sept. 2009