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A Physics-Based Compact Model of III–V FETs for Digital Logic Applications: Current–Voltage and Capacitance–Voltage Characteristics

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2 Author(s)
Saeroonter Oh ; Dept. of Electr. Eng., Stanford Univ., Stanford, CA, USA ; H. -S. Philip Wong

A physics-based analytical compact model of InGaAs field-effect transistors (FETs) for digital logic applications is developed. This model neither heavily depends on parameter extraction nor requires any time-consuming computation while capturing the essential physics, enabling digital circuit design and circuit-level performance estimation for III-V FETs. The model captures short channel effects, trapezoidal-shape quantum-well energies, bias-dependent ballistic ratios, and capacitances including 2D potential profile information. Each is verified via numerical calculations and 2D electrostatic simulation, followed by a comparison of the model I-V characteristics with experiment data. Finally, the transient response of FO4 inverters demonstrates the use of the compact model for future technology circuit simulations.

Published in:

IEEE Transactions on Electron Devices  (Volume:56 ,  Issue: 12 )