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TCAD/Physics-Based Analysis of High-Density Dual-BOX FD/SOI SRAM Cell With Improved Stability

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6 Author(s)
Keunwoo Kim ; IBM T.J. Watson Res. Center, Yorktown Heights, NY, USA ; Jente B. Kuang ; Fadi H. Gebara ; Hung C. Ngo
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This paper presents a new SRAM cell using a global back-gate bias scheme in dual buried-oxide (BOX) FD/SOI CMOS technologies. The scheme uses a single global back-gate bias for all cells in the entire columns or subarray, thereby reducing the area penalty. The scheme improves 6T SRAM standby leakage, read stability, write ability, and read/write performance. The basic concept of the proposed scheme is discussed based on physical analysis/equation to facilitate device parameter optimization for SRAM cell design in back-gated FD/SOI technologies. Numerical 2-D mixed-mode device/circuit simulation results validate the merits and advantages of the proposed scheme.

Published in:

IEEE Transactions on Electron Devices  (Volume:56 ,  Issue: 12 )