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High Performance Analog to Digital Converter in CCD Image Processor

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2 Author(s)
Mei-hua Xu ; Coll. of Mechatron. Eng. & Autom., Shanghai Univ., Shanghai, China ; Yu-le Fan

This paper presents a low-power consumption, 10 bit and 90 Ms/s pipeline ADC for a CCD image processor. The decrease of power consumption is achieved by employing OPAMP sharing technique and optimization factor based capacitor scaling technique. The ADC is implemented in TSMC 0.18 mum 1P6M CMOS process, and the experimental results indicate that it achieves an ENOB of 9.2 bit, a maximum DNL of 0.46 LSB, a maximum INL of 0.83 LSB for a 1.3 MHz 2.2 Vpp sinusoid input at full sampling rate. The total power consumption of the ADC core is only 39.4 mW from a 3.3 V supply. The whole ADC layout occupies 1.1 mm2.

Published in:

Image and Signal Processing, 2009. CISP '09. 2nd International Congress on

Date of Conference:

17-19 Oct. 2009