A 900-mV Area-Efficient Source-Degenerated CMOS Four-Quadrant Multiplier with 10.6-GHz Bandwidth

This paper presents a low-voltage area-efficient four-quadrant CMOS multiplier reconfigured in a source-degenerated topology and designed as a part of a correlator for an integrated ultra-wideband (UWB) transceiver. The simulation based on a 0.18-mum CMOS technology shows that the multiplier offers 10.6-GHz bandwidth while dissipating 290 muA from a 0.9-V supply.