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A 900-mV Area-Efficient Source-Degenerated CMOS Four-Quadrant Multiplier with 10.6-GHz Bandwidth

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3 Author(s)
Yuwono, S. ; Dept. of Inf. Commun. Eng., KAIST, Daejeon, South Korea ; Sok-Kyun Han ; Sang-Gug Lee

This paper presents a low-voltage area-efficient four-quadrant CMOS multiplier reconfigured in a source-degenerated topology and designed as a part of a correlator for an integrated ultra-wideband (UWB) transceiver. The simulation based on a 0.18-mum CMOS technology shows that the multiplier offers 10.6-GHz bandwidth while dissipating 290 muA from a 0.9-V supply.

Published in:

Wireless Communications, Networking and Mobile Computing, 2009. WiCom '09. 5th International Conference on

Date of Conference:

24-26 Sept. 2009