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Implementing macro test in silicon compiler design

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4 Author(s)
Beenker, F. ; Philips Res. Lab., Eindhoven, Netherlands ; Dekker, R. ; Stans, R. ; Van der Star, M.

A testability strategy for a complex VLSI device that is implemented in the Piramid digital-signal-processor silicon compiler is presented. The macro test method proposed supports built-in self-test, scan test, restricted partial scan, and test-control logic at various levels in the design hierarchy. The strategy uses techniques such as a macro test plan, transfer information, and intermediate vector storage. The overhead from adding testability is only 10% of the total area and test-program generation is done with 100% fault coverage in a very short time, since there is no need for global test-pattern generation. A set of tools that guide the testability implementation from design to the final test program is described.<>

Published in:

Design & Test of Computers, IEEE  (Volume:7 ,  Issue: 2 )

Date of Publication:

April 1990

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