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Low-cost testing of high-density logic components

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8 Author(s)
Bassett, R.W. ; IBM Corp., Essex Junction, VT, USA ; Butkus, B.J. ; Dingle, S.L. ; Faucher, M.R.
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The evolution of a testing method and architecture of a logic-device tester to be used for the next generation of IBM's high-density CMOS ASIC (application-specific integrated circuit) logic components is described. The tester's design is based on the architecture of an existing IBM memory tester rather than on a conventional logic-tester design. The testing strategy calls for boundary-scan in each component design, built-in self-test logic within embedded memory arrays, and the use of weighted random-pattern logic testing. The development of the tester hardware is discussed, and capital costs of the new tester are compared with those of other approaches.<>

Published in:

Design & Test of Computers, IEEE  (Volume:7 ,  Issue: 2 )