A Functional Model of SystemC-Based MPEG-2 Decoder with Heterogeneous Multi-IP-Cores and Hybrid-Interconnections Architecture

In this paper, a functional model of SystemC-based MPEG-2 decoder is presented, which is of heterogeneous multi-IP-cores and hybrid-interconnections. Considering the application-specific features into the design flow, three important aspects are analyzed, including function partition, parameter sharing, and interconnection topology, which are the key technical difficulties in the system level design of a video decoder. A kind of function unit determination is proposed on account of the balance of traffic load on the communication sub-system onchip. At the same time, to be able to charge with the heavy transmission burden, a hybrid interconnection with bus and point-to-point (P2P) is applied. Additionally, in order to enhance the decoder performance, high-frequently transmitted and updated parameters are extracted to store in on-chip shared memories. The presented application-specific architecture is proofed to be efficient with a system level model on SystemC-based environments. More, the topology and design flow would be a guideline for the design of such application-specific system-on-chip (SoC), and set up a quick evaluation method.